Conventionally, the bonding of a semiconductor chip or optical element chip (hereinafter, referred to as a “chip”) on a substrate involves aligning the chip on a predetermined position. In order to improve accuracy of alignment, various apparatuses and methods have been proposed. As an example of such conventional apparatuses and methods, an alignment index is formed on at least one of a chip surface and a substrate surface (see Patent Publication 1: Japanese Laid-Open Patent Publication No. 8-83955 (published on Mar. 26, 1996), for example).
In the apparatus and method of Patent Publication 1, an alignment index is formed that is defined by an inclined plane with respect to the chip surface and/or substrate surface, and the inclined plane defining a hole or trench is completely covered with the chip or substrate surface when the chip is mounted on the substrate. This creates a sealed space between the inclined plane and the chip or substrate surface. In some cases, the substrate with the chip bonded thereon is processed under high temperature conditions. Here, if there is a sealed space between the substrate and the chip, the temperature of the gas trapped in the space raises during the high-temperature process and the pressure therein is increased. The problem of the apparatus and method described in Patent Publication 1, then, is that the increased pressure in the sealed space created by the inclined plane defining the alignment index acts to detach the chip from the substrate.